Three dimensional multilayer circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 30, 2013
Grant Date -
Mar 31, 2011
app pub date -
Sep 25, 2009
filing date -
Sep 25, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template is then aligned with the first set of vias and lower crossbar segments are created using the template. The template is then removed, rotated, and aligned with the set of second vias. Upper crossbar segments which attach to the second set of vias are then created.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully