Method for assuring counterbore depth of vias on printed circuit boards and printed circuit boards made accordingly

United States of America Patent

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Apr 30, 2013
Grant Date
Dec 16, 2010
app pub date
Jun 16, 2009
filing date
Jun 16, 2009

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Abstract

A method is disclosed for fabricating a PCB so that is can easily be determined if a via in the PCB has not been counterbored to a desired depth. A PCB fabricated according to the method also is disclosed.

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Patent Owner	Address
CIENA CORPORATION	7035 RIDGE ROAD HANOVER MD 21076

International Classification(s)

H05K:PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAIL....

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Inventor Name	Address	# of filed Patents	Total Citations
McDonald, Robert	Ontario, CA	46	587
Twardy, Craig	Quebec, CA	2	27

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Method for assuring counterbore depth of vias on printed circuit boards and printed circuit boards made accordingly

Number of patents in Portfolio can not be more than 2000

United States of America Patent

12485375

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PATENT NO	8431834
APP PUB NO	20100314163A1
SERIAL NO	12485375
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
April 30, 2013	US,8431834,B2 US8431834B2	GRANTED PATENT AS SECOND PUBLICATION
December 16, 2010	US,20100314163,A1 US20100314163A1	FIRST PUBLISHED PATENT APPLICATION

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12485375

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