Methodology for fabricating isotropically recessed drain regions of CMOS transistors
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United States of America Patent
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Apr 30, 2013
Grant Date -
Nov 17, 2011
app pub date -
May 13, 2010
filing date -
May 13, 2010
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Abstract
A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
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