Clocked inverter, NAND, NOR and shift register
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United States of America Patent
Stats
-
Apr 30, 2013
Grant Date -
Apr 12, 2012
app pub date -
Oct 12, 2011
filing date -
Sep 25, 2002
priority date (Note) -
In Force
status (Latency Note)
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Abstract
In a display device including a substrate, a pixel portion, and a driver circuit having first to ninth transistors and first and second inverters, the various transistors are configured such that one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor. In embodiments, the electrical connection may be a direct connection. Additionally, a switch may be provided that is directly connected to an output terminal of the second inverter.
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