Detection of word-line leakage in memory arrays
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United States of America Patent
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Apr 30, 2013
Grant Date -
Jan 12, 2012
app pub date -
Jul 9, 2010
filing date -
Jul 9, 2010
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Abstract
Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit.
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