Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 30, 2013
Grant Date -
Jun 24, 2010
app pub date -
Mar 3, 2010
filing date -
May 17, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully