Semiconductor memory device capable of memorizing multivalued data
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United States of America Patent
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Apr 30, 2013
Grant Date -
Nov 22, 2012
app pub date -
Aug 6, 2012
filing date -
Nov 11, 2005
priority date (Note) -
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Abstract
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.
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