Multi-column addressing mode memory system including an integrated circuit memory device
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United States of America Patent
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Apr 30, 2013
Grant Date -
Jul 5, 2012
app pub date -
Mar 1, 2012
filing date -
Sep 30, 2004
priority date (Note) -
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Abstract
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
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