Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
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United States of America Patent
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Apr 30, 2013
Grant Date -
Feb 19, 2009
app pub date -
Aug 16, 2007
filing date -
Aug 16, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.
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