Address assignment and type recognition of serially interconnected memory devices of mixed type
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United States of America Patent
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Apr 30, 2013
Grant Date -
Jun 12, 2008
app pub date -
Jun 29, 2007
filing date -
Dec 6, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and an input serial interface for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, flash memory (e.g., NAND- and NOR-type flash memories). In an initialization phase, the memory devices are assigned with consecutive number addresses. The memory controller sends a target address and can recognize the type of the targeted memory device. A data path for the memory commands and the memory responses is provided by the interconnection.
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