Instruction sequence verification to protect secured data
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United States of America Patent
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Apr 30, 2013
Grant Date -
Jun 12, 2008
app pub date -
Jan 28, 2008
filing date -
May 30, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected. Preferably, the controller is reset if the first instruction is not a valid instruction from/to which the instruction sequence can be redirected.
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