Master reset and synchronizer circuit with data and clock inputs
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United States of America Patent
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Apr 30, 2013
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N/A
app pub date -
Jul 17, 2012
filing date -
Mar 21, 2005
priority date (Note) -
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Abstract
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.
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