Semiconductor test apparatus and test method

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United States of America Patent

PATENT NO 8433990
APP PUB NO 20100161264A1
SERIAL NO

12602144

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Abstract

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In a semiconductor test apparatus, a voltage source generates a power supply voltage to be supplied to a DUT. A decision processor makes the DUT execute a predetermined test sequence. A noise generator superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the DUT, while the test sequence is being executed. The noise generator superimposes a noise voltage synchronized with a clock signal to be supplied to the DUT.

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Patent Owner(s)

Patent OwnerAddress
ADVANTEST CORPORATION1-6-2 MARUNOUCHI CHIYODA-KU TOKYO 1000005 ?1000005

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Matsumoto, Mitsuo Tokyo, JP 57 641

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