Specifying placement and routing constraints for security and redundancy
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United States of America Patent
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Apr 30, 2013
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N/A
app pub date -
Dec 14, 2010
filing date -
Jan 28, 2010
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Abstract
A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.
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