Multi-level clock gating circuitry transformation
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United States of America Patent
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Apr 30, 2013
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N/A
app pub date -
Jan 25, 2011
filing date -
May 29, 2007
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Abstract
A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
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