Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

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United States of America Patent

PATENT NO 8435836
APP PUB NO 20110111561A1
SERIAL NO

13007002

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Abstract

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Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farnworth, Warren M Nampa, US 855 33798
Fay, Owen R Meridian, US 120 968
Hembree, David R Boise, US 393 15928

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