Implementing semiconductor SoC with metal via gate node high performance stacked transistors
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United States of America Patent
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May 7, 2013
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Jul 12, 2012
app pub date -
Jan 12, 2011
filing date -
Jan 12, 2011
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Abstract
A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.
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