Stub minimization for multi-die wirebond assemblies with parallel windows
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United States of America Patent
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May 7, 2013
Grant Date -
Apr 4, 2013
app pub date -
Dec 27, 2011
filing date -
Oct 3, 2011
priority date (Note) -
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Abstract
A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.
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