Dual-edge register and the monitoring thereof on the basis of a clock
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 7, 2013
Grant Date -
Dec 8, 2011
app pub date -
Jun 2, 2011
filing date -
Jun 4, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully