Digital PLL circuit and clock generating method
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United States of America Patent
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May 7, 2013
Grant Date -
Sep 27, 2012
app pub date -
Mar 13, 2012
filing date -
Mar 22, 2011
priority date (Note) -
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Abstract
A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.
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