Single-trigger low-energy flip-flop circuit
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United States of America Patent
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May 7, 2013
Grant Date -
Nov 1, 2012
app pub date -
Apr 27, 2011
filing date -
Apr 27, 2011
priority date (Note) -
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Abstract
One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
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