Importance

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Abstract

This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration.

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First Claim