Digital frequency locked delay line
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United States of America Patent
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May 7, 2013
Grant Date -
Mar 15, 2012
app pub date -
Nov 17, 2011
filing date -
Aug 5, 2004
priority date (Note) -
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Abstract
A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
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