Adaptive precision arithmetic unit for error tolerant applications
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United States of America Patent
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May 7, 2013
Grant Date -
Apr 2, 2009
app pub date -
Sep 28, 2007
filing date -
Sep 28, 2007
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Abstract
Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.
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