Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
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United States of America Patent
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May 7, 2013
Grant Date -
Feb 18, 2010
app pub date -
Oct 5, 2009
filing date -
Jun 25, 2007
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Abstract
Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.
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