Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8438344
APP PUB NO 20110225475A1
SERIAL NO

12774861

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

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Patent Owner(s)

Patent OwnerAddress
TEXAS INSTRUMENTS INCORPORATED12500 TI BOULEVARD M/S 3999 DALLAS TX 75243

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dutta, Amit Kumar Bangalore, IN 21 139
Kumar, Sanjay Bangalore, IN 231 3420
Parekhji, Rubin A Bangalore, IN 18 329
Ravi, Srivaths Bangalore, IN 18 593

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