Apparatus for designing semiconductor integrated circuit, method of designing semiconductor integrated circuit, and program for designing semiconductor integrated circuit
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United States of America Patent
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May 7, 2013
Grant Date -
Dec 29, 2011
app pub date -
Feb 19, 2010
filing date -
Mar 3, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position determination so as to insert the trailing edge FF, and connecting a clock line to the FF based on the results of the determining section, and a buffer insertion section for inserting the buffer into the hold error section subjected to the position determination so as to insert the FF based on the results of data of the determining section.
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