Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions
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United States of America Patent
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May 7, 2013
Grant Date -
Mar 29, 2012
app pub date -
Sep 23, 2010
filing date -
Sep 23, 2010
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Abstract
Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.
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