Interface control for improved switching in RRAM
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United States of America Patent
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May 14, 2013
Grant Date -
Dec 15, 2011
app pub date -
Jun 11, 2010
filing date -
Jun 11, 2010
priority date (Note) -
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Abstract
A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.
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