Apparatus and method for decoupling asynchronous clock domains
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United States of America Patent
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May 14, 2013
Grant Date -
May 3, 2012
app pub date -
Oct 27, 2010
filing date -
Oct 27, 2010
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Abstract
A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.
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