Source and drain feature profile for improving device performance
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United States of America Patent
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May 21, 2013
Grant Date -
Nov 1, 2012
app pub date -
Jul 9, 2012
filing date -
Jun 30, 2010
priority date (Note) -
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Abstract
An integrated circuit device is disclosed. The disclosed device provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device disclosed herein has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a {100} crystallographic plane of the substrate.
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