Quasi-vertical structure for high voltage MOS device
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United States of America Patent
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May 21, 2013
Grant Date -
Sep 2, 2010
app pub date -
Feb 3, 2010
filing date -
Feb 27, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.
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