Importance

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Abstract

The present invention provides a multilayer wiring capable of reducing the area of the wiring layer while preventing the property deterioration due to the parasitic capacitance, a semiconductor device, a substrate for display device, and a display device. The multilayer wiring of the present invention includes: a first conductor; a second conductor; and a third conductor. The first conductor is positioned in a (n+1)th conductive layer. The second conductor is positioned in a (n+2)th conductive layer, is electrically connected to a conductor in a layer below the (n+1)th conductive layer through at least a first connection hole in a (n+1)th insulating layer directly below the (n+2)th conductive layer, and is positioned so as not to overlap with the first conductor in a plan view of the main face of the substrate. The third conductor is positioned in a (n+3)th conductive layer, is electrically connected to a second conductor through a second connection hole in a (n+2)th insulating layer directly below the (n+3)th conductive layer, and is positioned on the second connection hole toward the first conductor. The second connection hole overlaps with the first connection hole in a plan view of the main face of the substrate.

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First Claim