Chip stack package
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United States of America Patent
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May 21, 2013
Grant Date -
Dec 29, 2011
app pub date -
Sep 2, 2011
filing date -
Oct 30, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.
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