Stackable wafer level package and fabricating method thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8446017
APP PUB NO 20110068427A1
SERIAL NO

12562387

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Abstract

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A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.

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Patent Owner(s)

Patent OwnerAddress
AMKOR TECHONOLOGY KOREA INC280-8 SUNGSU 2GA 3 DONG SUNGDONG-GU SEOUL

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Chang Deok Uijeongbu-si, KR 9 265
Paek, Jong Sik Seoul, KR 103 1522
Park, In Bae Seoul, KR 19 261

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