FPGA RAM blocks optimized for use as register files
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United States of America Patent
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May 21, 2013
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app pub date -
May 3, 2012
filing date -
May 5, 2011
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Abstract
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
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