Time-shared latency locked loop circuit for driving a buffer circuit
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United States of America Patent
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May 21, 2013
Grant Date -
Dec 8, 2011
app pub date -
Jun 7, 2010
filing date -
Jun 7, 2010
priority date (Note) -
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Abstract
In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.
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