Nonvolatile memory devices with common source line voltage compensation and methods of operating the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 21, 2013
Grant Date -
Aug 4, 2011
app pub date -
Jan 26, 2011
filing date -
Feb 1, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully