Importance

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Abstract

Control bits for switches of a butterfly network are directly solved iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus index leading into the butterfly network are generated. A linear order bus index and a physical address are determined for a switch having an unsolved control bit. The solved control bits are applied to solve control bits to a next functional column in a linear and an interleaved order by starting from the bus index and physical address. The linear order is moved to the interleaved order by a reduced turbo de-interleaver and the interleaved order is moved to the linear order by a reduced turbo interleaver until solving a sequence of control bits related to the start bus index and the start physical address.

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First Claim