Method of fabricating a sealing structure for high-k metal gate
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United States of America Patent
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May 28, 2013
Grant Date -
Sep 6, 2012
app pub date -
May 7, 2012
filing date -
Aug 25, 2008
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
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