Method for stacked contact with low aspect ratio

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United States of America Patent

PATENT NO 8450200
APP PUB NO 20110092019A1
SERIAL NO

12973707

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Abstract

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A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Jye-Yen Taichung, TW 39 278
Wan, Wen-Kai Hsin-Chu, TW 17 249
Yao, Chih-Hsiang Taipei, TW 40 579
Yeh, Chen-Nan Hsi-Chih, TW 46 2624
Yu, Chen-Hua Hsin-Chu, TW 2207 47923

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