Method and apparatus for memory cell layout

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United States of America Patent

PATENT NO 8450778
APP PUB NO 20120049374A1
SERIAL NO

12862387

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Abstract

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A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTDHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Jacklyn San Ramon, US 28 96
Hsu, Kuoyuan San Jose, US 36 169
Tao, Derek C Fremont, US 52 691

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