Method of manufacturing semiconductor device including wiring layout and semiconductor device
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United States of America Patent
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May 28, 2013
Grant Date -
Nov 25, 2010
app pub date -
Apr 30, 2010
filing date -
May 19, 2009
priority date (Note) -
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Abstract
A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 μm or greater, executing one of etching the second wiring layer to set a width of 1.0 μm or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 μm or greater between adjacent portions of the first wiring layer and the second wiring layer.
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