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Abstract

A resistance control method for a nonvolatile variable resistive element in a nonvolatile semiconductor memory device is provided. The device includes a memory cell array in which unit memory cells having nonvolatile variable resistive elements and transistors are arranged in a matrix. The memory cells that are targets of a memory operation are selected by first selection lines (word lines), second selection lines (bit lines) and third selection lines (source lines). The method includes steps of selecting one or more first selection lines, selecting a plurality of second selection lines, and applying a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation, such that the voltage necessary for the memory operation is applied to all of the selected memory cells.

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First Claim