Pair bit line programming to improve boost voltage clamping
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United States of America Patent
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May 28, 2013
Grant Date -
May 24, 2012
app pub date -
Jan 27, 2012
filing date -
Oct 30, 2008
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Abstract
A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.
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