Multiplexing circuit for high-speed, low leakage, column-multiplexing memory devices
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United States of America Patent
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May 28, 2013
Grant Date -
Apr 19, 2012
app pub date -
Oct 15, 2010
filing date -
Oct 15, 2010
priority date (Note) -
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Abstract
A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.
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