Layered chip package and method of manufacturing same
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United States of America Patent
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Jun 4, 2013
Grant Date -
Nov 3, 2011
app pub date -
Apr 28, 2010
filing date -
Apr 28, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.
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