Method of plating through wafer vias in a wafer for 3D packaging
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United States of America Patent
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Jun 4, 2013
Grant Date -
May 31, 2012
app pub date -
Sep 28, 2009
filing date -
Oct 10, 2008
priority date (Note) -
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Abstract
A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil.
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