Overlay mark enhancement feature
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United States of America Patent
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Jun 4, 2013
Grant Date -
Jun 21, 2012
app pub date -
Feb 29, 2012
filing date -
Aug 11, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.
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