Method for reducing chip warpage
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 4, 2013
Issued Date -
N/A
app pub date -
Sep 22, 2011
filing date -
Nov 12, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully